1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device including a metal gate electrode and a method of manufacturing the same.
2. Description of the Related Art
With the progress of the generation of the transistors, scaling based on miniaturization is continuously carried out. On the International Technology Roadmap for Semiconductors (ITRS), a gate length (Lg) of 20 nm or less is expected in the transistor called the 32 nm half pitch (hp) technology generation. For the transistors of this 32 nm-generation, an Effective Oxide Thickness (EOT) of a gate insulating film needs to be scaled for the purpose of ensuring a driving ability (Ids) in correspondence to the scaling of the gate length. Moreover, a depth (Xj) of a diffusion layer also needs to be scaled for the purpose of suppressing a Short Channel Effect (SCE).
A technique for suppressing gate depletion by introducing a metal gate electrode instead of using a polysilicon gate electrode as well as for introducing a high-permittivity (High-k) insulating film as the gate insulating film instead of using a silicon oxide film is investigated as the technique for scaling the effective oxide thickness of the gate insulating film of those techniques.
Here, a material used for the metal gate electrode, for example, tungsten (W), titanium (Ti), hafnium (Hf), ruthenium (Ru) or iridium (Ir) is a material having a high reactive property. For this reason, when a heat treatment is carried out for this sort of material at a high temperature, this sort of material reacts with a gate insulating film, thereby deteriorating a film quality of the gate insulating film. Therefore, a process is preferably adopted such that after completion of the formation of the metal gate electrode, no heat treatment is carried out for the metal gate electrode at the high temperature. One of methods for realizing this process, a buried gate process (a so-called damascene gate process) shown in FIGS. 2A to 2K is proposed. This technique, for example, is described in a non-patent literary document of Atsushi Yagishita et al.: “High Performance Metal Gate MOSFETs Fabricated by CMP for 0.1 μm Regime,” International Electron Devices Meeting 1998 Technical Digest pp. 785 to 788 (1998).
In the buried gate process, firstly, as shown in FIG. 2A, a dummy gate 3 made of polysilicon (poly-Si), and a hard mask layer 4 are formed in a lamination form on a semiconductor substrate 1 through a dummy gate insulating film 2. Next, sidewall insulating layers including a spacer insulating film 5a made from either a silicon oxide film or a silicon nitride film, a first sidewall insulating film 5b, and a second sidewall insulating film 5c are formed on sidewalls of the dummy gate 3 and the hard mask layer 4. In addition, a source and a drain 1sd are formed on a surface side of the semiconductor substrate 1, and a silicide layer 6 is then formed on the surface side of the substrate 1.
Next, as shown in FIG. 2B, a liner insulating film 7 made of a silicon nitride is formed above the semiconductor substrate 1, and an interlayer insulating film 8 made of a silicon oxide (SiO2) is formed so as to cover the liner insulating film 7. After that, as shown in FIG. 2C, the interlayer insulating film 8, the liner insulating film 7, and the hard mask layer 4, and the like are polished in order by utilizing a CMP (Chemical Mechanical Polishing) method, thereby exposing the dummy gate 3. Next, as shown in FIG. 2D, the dummy gate 3 and the dummy gate insulating film 2 are selectively etched away in order, thereby forming a trench pattern a for formation of a gate electrode.
Next, as shown in FIG. 2E, a gate insulating film 9 made of a high-permittivity material (for example, a hafnium oxide (HfO2)) such as a metallic oxide film or a metallic nitride film is deposited so as to cover an inner wall of the trench pattern a. Next, as shown in FIG. 2F, an electrode material film obtained by laminating a first base electrode material film 10a made of a hafnium silicide (HfSix), a second base electrode material film 10b made of a titanium nitride (TiN), and a main electrode material film 10c made of tungsten (W) in order is deposited so as to be filled in the trench pattern a.
After that, as shown in FIG. 2G, the main electrode material film 10c, the second base electrode material film 10b, and the first base electrode material film 10a are polished in order by utilizing the CMP method, thereby forming a gate electrode 10 with the first base electrode material film 10a, the second base electrode material film 10b, and the main electrode material film 10c being left only in the trench pattern a. After that, as shown in FIG. 2H, an upper layer insulating film 11 made of a silicon oxide (SiO2) is formed above the semiconductor substrate 1 so as to cover the gate electrode 10. After that, as shown in FIG. 2I, the upper layer insulating film 11 is selectively etched away into a predetermined pattern, thereby forming a connection hole 11a reaching the gate electrode 10.
Next, as shown in FIG. 2J, after etching using a hydrofluoric acid is carried out as a pretreatment for a next film deposition process, a conductive material film obtained by laminating a base conductive film 12a and a main conductive film 12b in order is deposited so as to be filled in the connection hole 11a. After that, as shown in FIG. 2K, the main conductive film 12b and the base conductive film 12a are polished in order by utilizing the CMP method, thereby forming a contact plug 12 with the base conductive film 12a and the main conductive film 12b being left only in the connection hole 11a. After completion of the above process, a wiring (not shown) is formed on the upper layer insulating film 11 so as to be connected to the contact plug 12.